sys32128zk/lk - 010/012/015/017 issue 1.3 january 1999 1 pin definition address inputs a0 - a16 data input/output d0 - d31 chip selects cs1~4 write enable we output enable oe no connect nc presence detect pd0~1 power (+5v) v cc ground gnd block diagram description features 128k x 32 sram module sys32128zk/lk - 010/012/015/017 issue 1.3 : january 1999 pin functions d0-d7 d8-d15 d16-d23 d24-d31 a0-a16 oe we cs1 cs2 cs3 cs4 128kx8 sram 128kx8 sram 128kx8 sram 128kx8 sram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 gnd pd0 pd1 d0 d8 d1 d9 d2 d10 d3 d11 vcc a0 a7 a1 a8 a2 a9 d12 d4 d13 d5 d14 d6 d15 d7 gnd we a15 a14 cs2 cs1 cs4 cs3 nc a16 oe gnd d24 d16 d25 d17 d26 d18 d27 d19 a3 a10 a4 a11 a5 a12 vcc a13 a6 d20 d28 d21 d29 d22 d30 d23 d31 gnd oe cs2 cs4 cs3 a16 gnd d16 d17 d18 d19 a10 a11 a12 a13 d20 d21 d22 d23 gnd pd0 d0 d1 d2 d3 vcc a7 a8 a9 d4 d5 d6 d7 we a14 cs1 gnd pd1 d8 d9 d10 d11 a0 a1 a2 d12 d13 d14 d15 gnd a15 nc d24 d25 d26 d27 a3 a4 a5 vcc a6 d28 d29 d30 d31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 zip the sys32128zk/lk is a plastic 4mbit static ram module offered in 64 pin zip and 64 lead simm packages, organised as 128k x 32. the module utilises four fast 128kx8 srams housed in soj packages, surface mounted onto an fr4 epoxy pcb. four chip selects are used to independently enable the four bytes. reading or writing is executed on individual or any combination of multiple bytes. two pins pd0 & pd1 are used to identify module memory density where alternative versions of the jedec standard modules can be interchanged. plastic 64 pin jedec zip plastic 64 pin jedec simm package details simm ? access times of 10/12/15/17 ns. ? 64 pin zip & simm standard pinouts. ? 5 volt supply 10%. ? power dissipation : operating (10ns) 5.5 w (maximum). standby (cmos) -l 44mw (maximum). ? completely static operation. ? equal access and cycle times. ? on-board supply decoupling capacitors. ? data retention capability. (-l version only). 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
issue 1.3 january 1999 sys32128zk/lk - 010/012/015/017 2 parameter symbol test condition typ max unit input capacitance (cs1~4) c in1 v in = 0v - 8 pf input capacitance (other) c in2 v in = 0v - 32 pf i/o capacitance c i/o v i/o = 0v - 8 pf parameter symbol min typ max unit dc operating conditions absolute maximum ratings (1) parameter symbol min typ max unit voltage on any pin relative to v ss v t -0.5 - +7.0 v power dissipation p t - - 4.0 w storage temperature t stg -55 - +125 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (v cc =5v10%,t a =25 o c) note: capacitance calculated, not measured. dc electrical characteristics (v cc =5v10%) t a 0 to 70 o c recommended operating conditions supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - v cc +0.5 v input low voltage v il -0.5 (2) - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i) (2) v t can be -1.5 v pulse of less than 10 ns. parameter symbol test condition min typ max unit i/p leakage current i li v in = gnd to v cc -20 - 20 a output leakage current i lo cs = v ih, v i/o = gnd to v cc -20 - 20 a operating supply current i cc cs = v il, min cycle, 10ns - - 1000 ma 12ns - - 920 ma 100% duty, i i/o =0ma , 15ns - - 780 ma 17ns - - 720 ma standby supply current ttl levels i sb1 cs = v ih - - 280 ma -l (cmos levels) i sb cs = v cc -0.2v, 0.2 > v in > v cc -0.2v - - 80 ma output low voltage v ol i ol = 8.0ma - - 0.4 v output high voltage v oh i oh = -4.0ma 2.4 - - v typical values are at v cc =5.0v,t a =25 c and specified loading. all values specified for 32 bit operation. cs above refers to cs1~4 on the module.
sys32128zk/lk - 010/012/015/017 issue 1.3 january 1999 3 low v cc data retention characteristics - l version only parameter symbol test condition min typ max unit v cc for data retention v dr cs >v cc -0.2v 2.0 - - v data retention current i ccdr1 v cc =2.0v,cs >1.8v,t op =t a -- 3ma i ccdr2 v cc =3.0v,cs >2.8v,t op =t ai - - 3.5 ma chip deselect to data retention time t cdr see retention waveform 0- -ns operation recovery time t r see retention waveform t rc (1) --ns notes: (1) t rc =read cycle time operation truth table cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 standby l l h data out i cc read l x l data in i cc write l h h high impedance i cc output disabled notes : h = v ih : l =v il : x = v ih or v il ac test conditions output load * input pulse levels: 0 v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc = 5v 10% i/o pin 166 ohms 1.76 v 30pf
issue 1.3 january 1999 sys32128zk/lk - 010/012/015/017 4 read cycle (1) ac operating conditions write cycle -010 - 012 -015 -017 parameter symbol min max min max min max min max unit read cycle time t rc 10 - 12 - 15 - 17 - ns address access time t aa -10-12-15-17ns chip select access time t acs -10-12-15-17ns output enable to output valid t oe -6-6-8-9ns output hold from address change t oh 2-3-3-3-ns chip selection to output in low z t clz 0-0-0-0-ns output enable to output in low z t olz 0-0-0-0-ns chip deselection to o/p in high z (2) t chz 06060708ns output disable to output in high z (2) t ohz 06060607ns -010 -12 -15 -17 parameter symbol min max min max min max min max unit write cycle time t wc 10 - 12 - 15 - 17 - ns chip selection to end of write t cw 9 - 10 - 12 - 13 - ns address setup time t as 0-0-0-0-ns address valid to end of write t aw 9 - 10 - 12 - 13 - ns write pulse width t wp 7-9-12-13-ns write recovery time t wr 0-0-0-0-ns write to output in high z (3) t whz 06070809ns data to write time overlap t dw 6-7-8-9-ns data hold from write time t dh 0-0-0-0-ns output active from end of write t ow 0-0-0-0-ns
sys32128zk/lk - 010/012/015/017 issue 1.3 january 1999 5 read cycle timing waveform (1,2) (1) we is high for read cycle. (2) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. write cycle no.1 timing waveform (1-10) dw dh wp as aw cw don't care t t t t t t t t t wc wr ohz address oe cs1~4 we dout din hi g h-z hi g h-z ow t ohz olz aa acs clz oe oh chz data valid t t t t t t t t t rc address cs1~4 dout oe don't care.
issue 1.3 january 1999 sys32128zk/lk - 010/012/015/017 6 ac characteristics notes (1) a write occurs during the overlap (t wp ) of a low cs1~4 and a low we. (2) all write cycle timing is referenced from the last valid address to the first transition address. (3) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. (4) at any given temperature and voltage condition, t whz (max) is less than t ow (min) both for a given module and from module to module. (5) module is continuously selected with cs1~4 = v il . (6) cs1~4 or we must be high during address transition. (7) we is high for read cycle. (8) all read cycle timing is referenced from the last valid address to the first transition address. (9) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (10) address is valid prior to or coincident with cs1~4 transition low. write cycle no.2 timing waveform (1-10) cw wr wc as dw dh oh ow whz aw wp don't t t t t t t address cs1~4 we dout din t t t t t care high-z high-z data retention waveform t r t cdr 4.5v 4.5v data retention mode vcc v dr v ih v dr v il cs1~4 don't care
sys32128zk/lk - 010/012/015/017 issue 1.3 january 1999 7 speed 010 = 10ns 012 = 12 ns 015 = 15 ns 017 = 17 ns temperature range blank = commercial temp. i = industrial temp. power consumption blank = standard part l = low power part package zk = plastic 64 pin zip lk = plastic 64 pin simm organisation 32128 = 128k x 32 memory type sys = static ram package information dimensions in mm ordering information plastic 64 pin zig-zag-in-line package (zip) 5.85 max. 14.60 max 88.26 max. 2.54 typ. 6.35 typ. 2.54 typ. 4.00 3.20 1 plastic 64 pin single in-line memory module (simm) 97.92 max. 91.03 typ. 48.90 typ. 10.16 typ. 15.24 max. 5.59 sys32128 zk/lk li-010 note : although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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